Applied Materials reveals chip wiring innovations for energy-efficient computing
What innovations has Applied Materials introduced for chip wiring?
Applied Materials has introduced materials engineering innovations for chip wiring, enabling two-nanometer node manufacturing. The innovations reduce resistance in wiring by up to 25% and decrease chip capacitance by up to 3%. A new binary metal combination of ruthenium and cobalt (RuCo) is used, which reduces the thickness of the liner, produces better surface properties for void-free copper reflow, and improves chip performance and power consumption.
How do new materials affect chip resistance and capacitance?
New materials in chip wiring enable scaling to the 2nm node, reducing resistance by up to 25% and lowering chip capacitance by 3%. This is achieved through the use of enhanced low-k dielectrics, which surround copper wires with a low dielectric constant film, reducing electrical charge buildup and interference. Additionally, a new binary metal liner of ruthenium and cobalt reduces the thickness of the liner, improves surface properties for void-free copper reflow, and decreases electrical line resistance6.
What is the significance of the two-nanometer node in chip manufacturing?
The two-nanometer node in chip manufacturing represents a significant milestone in semiconductor technology. It enables the production of chips with increased transistor density, improved performance, and reduced power consumption compared to previous nodes. This breakthrough is crucial for advancing the state-of-the-art in the semiconductor industry and meeting the growing demand for energy-efficient computing in the era of hybrid cloud, AI, and the Internet of Things.